Microcontrollers generally are systems on a single chip and comprise a microcontroller core or central processing unit and a plurality of peripheral components. A wide variety of such microcontrollers exist having 8-bit, 16-bit and 32-bit architecture. Existing microcontrollers such as 8-bit microcontrollers manufactured by the Applicant Microchip Technology Inc. provide for a flexible architecture wherein a plurality of families are available, each family having a different complexity. Such microcontrollers may for example comprise a Harvard architecture in which program and data memories are separated. Microcontrollers of this type may further comprise a specific banking system that allows access to the data memory without a complex decoding circuitry. Generally, the data memory is divided in a plurality of banks and a bank select register defines which of the banks is currently selected and accessible. To access other banks, the bank select register has to be re-programmed. Even though such a banking scheme only allows access to a single defined memory bank, these controllers may include instructions that force a switch to a predefined bank. This provides for improved and powerful performance despite the general access limitations.
According to a product palette, different families of microcontrollers in an 8-bit family can be provided as mentioned above. For example, a baseline family might provide for only essential functionalities which allows manufacture of such devices at very low cost. For example, such a baseline product may not support interrupts wherein more advanced families may have these functionalities. Interrupt functionality can add significant circuitry which does not allow to manufacture such devices at very low costs.
As mentioned above, many microcontroller designs, in particular 8-bit microcontrollers, have a reduced functionality and therefore simplified architecture to save valuable silicon real estate and allow for a reduced chip size and thus for a higher number of chips per wafer. For example, according to Applicant Microchip Technology Inc.'s product line, many of so-called baseline 8-bit microcontroller's code execution is limited by lack of interrupt functions.
FIG. 1, shows a simplified block diagram of such a conventional microcontroller with a data memory that can be accessed with a banking mechanism. A program memory 110 stores a plurality of instructions forming an executable program. Program counter 115 may be designed to have for example 11 bits for addressing a 2 k linear program memory. A stack 120 may be provided to store program counter values when subroutines are executed. The shown exemplary microcontroller is an 8-bit Harvard-type microcontroller that operates with 12-bit instruction words stored in program memory 110. Thus, a central 8-bit data bus 105 may be used to couple various functional elements within the microcontroller, such as for example timer unit 0 and external port B 130. The data memory 125 is coupled with this bus 105 and receives for example an 8-bit address from address multiplexer 140. For direct addressing, address multiplexer 140 combines an address from address data supplied by the instruction register 135 and address data supplied by special function register 145. In direct addressing mode, the instruction register 135, thus, supplies the lower 5 bits and the special function register 145 the upper 3 bits. Thus, according to an embodiment, special function register 145 operates as a bank select register capable of selecting one of 8 different memory banks. In indirect addressing, special function register 145 provides for a complete address with all bits 0-7. Indirect addressing is implemented by accessing special function register INDF which is a virtual register and therefore not a physically implemented. Any read or write access to this register INDF forces that an indirect access is applied to the data memory 125 via special function register 145. Thus, instead of reading or writing register INDF, an indirect data memory access is performed.
According to this type of architecture, instruction register 135 receives an instruction directly from program memory 110 and is coupled with an instruction decode & control unit 180, for example, through another internal 8 bit bus. Instruction decode & control unit 180 is furthermore coupled with certain internal function provided by unit 175. For example, this functional unit 175 may include a device reset timer, a power-on reset, a watchdog timer, an internal RC clock, etc. Other functions can be integrated and/or certain functions may be omitted. Timing generation unit 185 may provide for internal timing signals and can also be coupled with unit 175. The conventional 8-bit microcontroller core shown in FIG. 1 has an arithmetic logic unit 160 (ALU) coupled with a status register 150. The ALU 160 is further coupled with a working register 165 and receives data from the instruction register 135 and the 8-bit data bus through multiplexer 155 on one hand and on the other hand from working register 165. FIG. 1, thus, merely shows some essential structure of a so-called baseline microcontroller core.
FIG. 2 shows an example of another block diagram of a microcontroller core that provides for more functionality. Generally, similar elements carry the same reference symbol. The data memory RAM 225 shown in FIG. 2 can be identical to the memory as shown in FIG. 1. However, a different reference symbol is used to indicate that this RAM 225 is differently mapped as will be explained below in more detail. This data memory now comprises a linear memory block consisting of a plurality of sequential memory banks to which no special function registers are mapped. An additional bank select register (BSR) 210 is provided wherein this register is accessible through a dedicated instruction and therefore may not be memory mapped. The content of this register 210 provides for the upper 3 bits of an address provided by address multiplexer 220 which receives the lower 5 bits from instruction register 135. The special function register FSR 145 may now be an 8-bit register which can be used for indirect addressing of the entire linear data memory independent of the currently selected memory bank. In other embodiments, this register can be limited to access the upper 4 banks that form the linear data memory by setting bit 7 permanently to “1”. However, this register does not provide for the bank select function per se anymore. Bank selection is effected only by writing a respective bank number into the non-memory mapped bank select register 210. Thus, even when a memory bank within the linear memory block is selected, the dedicated instruction allows for change to any other memory bank. Other internal structures of low cost microcontroller cores are possible and can be combined with the specific embodiments disclosed in the various embodiments as will be explained in more detail below.
As mentioned above, many low cost microcontroller cores do not provide for an interrupt functionality due to the increase in core logic. A simple interrupt logic 250 can be added to the architectures mentioned above as shown in FIG. 2, for example a single interrupt input INT can be provided which may initiate an interrupt from various sources, wherein software has to handle identification and management of interrupt related tasks. If such a simple interrupt logic 250 is implemented, then an interrupt service routine code must share common special function registers with main line code. Thus, certain registers, such as register 245, 165 and 150 need to be manually saved when entering an interrupt routine. Certain microcontrollers, for example, Applicant's microcontroller series PIC16F1xxx provide for an automatic save and restore function of context registers using so-called shadow registers. The shadow registers are special function registers merely for the purpose to save the current context. They are overwritten each time an interrupt is initiated and their content is written back to the respective context registers upon return from the interrupt routine. However, while this is an improvement, when adding interrupt capability, there exists a need for an even more improved automatic context switching that prevents the need to manually store and restore those registers and allows for further use of the saved context.